When arithmetic operations are executed by digital processing, division operations require a greater amount of time than any of the other three types of arithmetic operation. It has been proposed in the prior art to reduce the time required for division operation by executing division using a sequential processing method, whereby a simple algorithm is utilized such that during each of sequential processing steps, the magnitude of the divisor and that of the dividend (or of the partial residue) are compared, and the type of computation that is executed in the succeeding step is determined based on the results of that comparison. With such a method, as for the usual method of multiplication processing, a number of parallel operation circuits are utilized. However it is found in practice that it is difficult to utilize such a division method.
For this reason, a method of convergence division has been proposed in the prior art, which utilizes a high speed multiplier and an adder/subtractor. In the following description of this prior art method, and of embodiments of the present invention given hereinafter, it will be assumed that both the divisor and dividend (or partial residue) are normalized numbers, where the term "normalized number" as used herein refers to a fixed point number such as the fixed point portion (i.e. mantissa) of a number expressed in floating-point form. It will further be assumed that the divisor (designated in the following as D) is of the form 0.1xxxx. . .s, having N valid digits, where N is a finite number and where "x" represents a digit value which can be either 0 or 1. In this case, the divisor D can be expressed as (1-D.sub.m), where D.sub.m is a value which is equal to or smaller than 0.1. For the case in which D.sub.m =0.1, the quotient can be made equal to twice the dividend (or partial residue). With binary number operations, this can be done simply by a one-digit left-shift operation, so that it is not necessary to perform an actual division operation for this special case. However even if that special case is excluded from the following description, the description is still generally applicable.
Specifically, the division operation A/D (where A designates the dividend) can be mathematically transformed as follows: ##EQU1##
Generally, the number N of valid digits of the numeric value system is in the range 48 &lt;N&lt;52, for the case of double precision floating-point expression. Assuming that N is 52, then value D.sub.m.sup.64 in the denominator will be smaller than the lower limit set by the number of digits of N. Thus, D.sub.m.sup.64 is effectively equal to zero. The following approximation is therefore true: ##EQU2##
Thus, the division computation can be executed by adding one to the result of each computation of D.sub.m raised to the power 2.sup.(n-1), with this addition being performed for each item in the expression (in this case, therefore, six addition operations are required).
In the above, D.sub.m.sup.2n is obtained as the square of D.sub.m.sup.2(n-1). Since the most significant digit of D.sub.m will be zero, (1 +D.sub.m.sup.2n) can be obtained simply by changing that most significant digit to a value of one. In that case, it can be considered that in practice a negligible amount of computation time is required to obtain (1+D.sub.m.sup.2n). thus, division can be considered to be executed by one subtraction operation for obtaining D.sub.m, and 11 multiplication operations (i.e. the 5 multiplication operations for obtaining D.sub.m.sup.2 to D.sub.m.sup.32 and the six multiplication operations for the six items of equation (2)).
If extremely high speed multipliers are used, the total multiplication time required for the above operations is of the order of 1 to 2 microseconds, so that a comparatively high speed division apparatus can be implemented.
Such a prior art convergence type of division apparatus, made up of a subtractor, multipliers, and a control circuit, can be made comparatively small in circuit scale. However due to the large number of multipliers which are used, it is difficult to provide an extremely high speed division apparatus by such a method.